1. Field of the Invention
The present invention relates to an organic light emitting display and a method of driving the same, and more particularly, to an organic light emitting display and a method of driving the same, in which a driving frequency is lowered and at the same time a production cost is reduced.
2. Discussion of Related Art
Recently, various flat panel displays have been developed to substitute for a cathode ray tube (CRT) display because the CRT display is relatively heavy and bulky. The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display.
Among the flat panel displays, the organic light emitting display can emit light for itself by electron-hole recombination. Such an organic light emitting display has advantages in that response time is relatively fast and power consumption is relatively low. Generally, the organic light emitting display employs a thin film transistor (TFT) provided in each pixel for supplying a current corresponding to a data signal to a light emitting device, thereby allowing the light emitting device to emit light.
FIG. 1 illustrates a conventional organic light emitting display.
Referring to FIG. 1, a conventional organic light emitting display includes a display region 30 having a plurality of pixels 1 formed adjacent to respective regions where a plurality of scan lines S1 through Sn and a plurality of data lines D1 through Dm crossed each other, where n and m are natural numbers; a scan driver 20 adapted to drive the scan lines S1 through Sn; a data driver 10 adapted to drive the data lines D1 through Dm; and a controller 40 adapted to control the scan driver 20 and the data driver 10.
The scan driver 20 generates a scan signal(s) for driving the scan lines S1 through Sn in response to a scan control signal(s) GCS transmitted from the controller 40, and supplies the scan signals to the scan lines S1 through Sn in sequence.
The data driver 10 receives data control signals DCS and data Data from the controller 40. Then, the data driver 10 is controlled by the data control signals DCS to convert the data Data into voltage (or current), thereby outputting a data signal(s) to the data lines D1 through Dm. At this time, the data driver 10 supplies the data signal corresponding to one horizontal line per horizontal period to the data lines D1 through Dm.
In operation, a pixel 1 is selected when a scan signal is transmitted to a scan line S, and emits light corresponding to a data signal transmitted to a data line D. For this, each pixel 1 includes at least one switching device and a capacitor.
The controller 40 generates the data control signals DCS and the scan control signal(s) GCS in response to external synchronization signals. Here, the data control signals DCS are transmitted to the data driver 10, and the scan control signal GCS is transmitted to the scan driver 20.
Further, the controller 40 temporarily stores external data Data, and supplies the stored data Data to the data driver 10. For this, the controller 40 includes line memories 42 and 44 as shown in FIG. 2A. Additionally, the temporarily stored data Data can be supplied to a gamma generator (not shown). Then, the gamma generator generates the data signal in response to a gradation level of the data Data, and supplies the data signal to the data driver 10.
FIGS. 2A and 2B illustrate line memories provided in a controller of a conventional organic light emitting display.
Referring to FIGS. 2A and 2B, the controller 40 includes the first line memory 42 and the second line memory 44. Each of the line memories 42 and 44 is set to have a certain capacity to store data corresponding to one horizontal line. Here, the first line memory 42 and the second line memory 44 repeatedly alternate between writing and reading operations, alternately.
For example, as shown in FIG. 2A, while a writing signal W is transmitted to the first line memory 42, a reading signal R is transmitted to the second line memory 44. Here, the writing signal W and the reading signal R include various signals such as an address signal, a clock signal, etc. When the writing signal W is transmitted to the first line memory 42, the first line memory 42 stores external data Data corresponding to one horizontal line in sequence. Further, when the reading signal R is transmitted to the second line memory 44, the second line memory 44 supplies the data Data stored therein corresponding to one horizontal line to the data driver 10.
On the other hand, as shown in FIG. 2B, while the reading signal R is transmitted to the first line memory 42, the writing signal W is transmitted to the second line memory 44. When the reading signal R is transmitted to the first line memory 42, the first line memory 42 supplies the data Data stored therein corresponding to one horizontal line to the data driver 10. Further, when the writing signal W is transmitted to the second line memory 44, the second line memory 44 stores the external data Data corresponding to one horizontal line in sequence.
That is, the conventional organic light emitting display shown in FIG. 1 employs the line memories 42 and 44 to temporarily store the data Data and supply the stored data Data to the data driver 10, thereby displaying a predetermined image. Here, the line memories 42 and 44 store a plurality of data Data and supply the stored data Data to the data driver 10 per one horizontal period 1H, so that the reading signal R and the writing signal W have a high clock frequency.
Thus, because the clocks included in the reading signal R and the writing signal W have high frequency, an electromagnetic interference (EMI) or the like is generated, thereby deteriorating a driving operation of the organic light emitting display. Further, because each of the reading signal R and the writing signal W has the high clock frequency, a need arises for a high performance integrated circuit (IC) which can be stably driven at the high frequency, and thus a problem arises in that a production cost is increased. To solve this problem, there has been proposed an organic light emitting display as shown in FIG. 3.
FIG. 3 illustrates another conventional organic light emitting display. In FIG. 3, like numerals as those in FIG. 1 refer to like elements, and descriptions for elements that are substantially similar to those described above for the display of FIG. 1 will be avoided.
Referring to FIG. 3, the organic light emitting display includes a display region 30 having a plurality of pixels 1 formed adjacent to respective regions where a plurality of scan lines S1 through Sn and a plurality of data lines D1 through Dm crossed each other, where n and m are natural numbers; a scan driver 20 adapted to drive the scan lines S1 through Sn; a first data driver 12 adapted to drive odd numbered data lines D1, D3, . . . , Dm−1; a second data driver 14 adapted to drive even numbered data lines D2, D4, . . . , Dm; and a controller 50 adapted to control the scan driver 20, the first data driver 12, and the second data driver 14.
The scan driver 20 generates a scan signal(s) for driving the scan lines S1 through Sn in response to a scan control signal(s) GCS transmitted from the controller 50, and supplies the scan signals to the scan lines S1 through Sn in sequence.
The first data driver 12 receives data control signals DCS and odd numbered data Data(o) from the controller 50. Then, the first data driver 12 is controlled by the data control signals DCS to convert the odd numbered data Data(o) into voltage (or current), thereby outputting an odd numbered data signal(s) to the odd numbered data lines D1, D3, . . . , Dm−1. At this time, the first data driver 12 supplies the odd numbered data signal(s) corresponding to one horizontal line per horizontal period to the odd numbered data lines D1, D3, . . . , Dm−1.
In addition, the second data driver 14 receives the data control signals DCS and even numbered data Data(e) from the controller 50. Then, the second data driver 14 is controlled by the data control signals DCS to convert the even numbered data Data(e) into voltage (or current), thereby outputting an even numbered data signal(s) to the even numbered data lines D2, D4, . . . , Dm. At this time, the second data driver 14 supplies the even numbered data signal(s) corresponding to one horizontal line per horizontal period to the even numbered data lines D2, D4, . . . , Dm.
In operation, a pixel 1 is selected when a scan signal is transmitted to a scan line S, and emits light corresponding to a data signal transmitted to a data line D. For this, each pixel 1 includes at least one switching device and a capacitor.
The controller 50 generates the data control signals DCS and the scan control signal(s) GCS in response to external synchronization signals. Here, the data control signals DCS are transmitted to the first and second data drivers 12 and 14, and the scan control signal GCS is transmitted to the scan driver 20.
Further, the controller 50 temporarily stores external data Data as the odd numbered data Data(o) and the even numbered data Data(e), and supplies the stored odd numbered data Data(o) and the stored even numbered data Data(e) to the first and second data drivers 12 and 14, respectively. For this, the controller 50 includes line memory blocks 53 and 56 as shown in FIG. 4A. Additionally, the temporarily stored data Data can be supplied from the controller 50 to a gamma generator (not shown). Then, the gamma generator generates the data signal in response to a gradation level of the data Data, and supplies the data signal to the first and second data drivers 12 and 14.
FIGS. 4A and 4B illustrate line memories provided in a controller of a conventional organic light emitting display.
Referring to FIGS. 4A and 4B, the controller 50 includes the first line memory block 53 and the second line memory block 56. The first line memory block 53 includes a first memory 51 and a second memory 52. Each of the first and second memories 51 and 52 is set to have a certain capacity to store data corresponding to a half horizontal line. Here, the first memory 51 and the second memory 52 repeatedly alternate between writing and reading operations. Further, the second memory block 56 includes a third memory 54 and a fourth memory 55. Each of the third and fourth memories 54 and 55 is set to have a certain capacity to store data corresponding to a half horizontal line. Here, the third memory 54 and the fourth memory 55 repeatedly alternate between writing and reading operations.
For example, as shown in FIG. 4A, while a writing signal W is transmitted to the first and third memories 51 and 54, a reading signal R is transmitted to the second and fourth memories 52 and 55. When the writing signal W is transmitted to the first memory 51, the first memory 51 stores external odd numbered data Data(o) corresponding to one horizontal line in sequence. Further, when the writing signal W is transmitted to the third memory 54, the third memory 54 stores external even numbered data Data(e) corresponding to one horizontal line in sequence.
When the reading signal R is transmitted to the second memory 52, the second memory 52 supplies the odd numbered data Data(o) stored therein corresponding to one horizontal line to the first data driver 12. Here, the second memory 52 either outputs the odd numbered data Data(o) at the same time or in sequence. When the reading signal R is transmitted to the fourth memory 55, the fourth memory 55 supplies the even numbered data Data(e) stored therein corresponding to one horizontal line to the second data driver 14. Here, the fourth memory 55 either outputs the odd numbered data Data(e) at the same time or in sequence.
On the other hand, as shown in FIG. 4B, while the reading signal R is transmitted to the first and third memories 51 and 54, the writing signal W is transmitted to the second and fourth memories 52 and 55. When the reading signal R is transmitted to the first memory 51, the first memory 51 supplies the odd numbered data Data(o) stored therein for a previous horizontal period to the first data driver 12. When the reading signal R is transmitted to the third memory 54, the third memory 54 supplies the even numbered data Data(e) stored therein for the previous horizontal period to the second data driver 14.
When the writing signal W is transmitted to the second memory 52, the second memory 52 stores the external odd numbered data Data(o) therein corresponding to one horizontal line in sequence. When the writing signal W is transmitted to the fourth memory 55, the fourth memory 55 stores the even numbered data Data(e) therein corresponding to one horizontal line in sequence.
Thus, each of the conventional memories 51, 52, 54 and 55 stores odd or even numbered data Data(o) or Data(e), and supplies the stored odd or even numbered data Data(o) or Data(e) to the first data driver or the second data driver 12 or 14, so that the frequency of the clock included in the reading and writing signals R and W can be advantageously lowered by about half as compared with the organic light emitting display of FIG. 1. However, the conventional organic light emitting display of FIG. 3 is in need of different data drivers 12 and 14 to drive the odd numbered data lines D1, D3, . . . , Dm−1 and the even numbered data lines D2, D4, . . . , Dm, so that the picture quality may be deteriorated.
In more detail, the first data driver 12 and the second data driver 14 have to supply the odd numbered data signal and the even numbered data signal at the same time. However, the data control signals DCS are not transmitted to the first and second data drivers 12 and 14 at the same time due to line resistance or the like, and thus the odd numbered data signal and the even numbered data signal are transmitted at different times. Because as the odd numbered data signal and the even numbered data signal are not supplied at the same time, the picture quality is deteriorated by a unit of a vertical line.
Further, the odd numbered data lines D1, D3, . . . , Dm−1 and the even numbered data lines D2, D4, . . . , Dm are driven by the different data drivers 12 and 14, so that interference arises due to a capacitance equivalently formed between adjacent data lines D, and the picture quality may be further deteriorated.